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ControlUnit.hxx
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1995-07-26
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///////////////////////////////////////////////////////////////////////////////
//
// ControlUnit.hxx - Control Unit for the Hector 1600 CPU
//
// By: Bradford W. Mott
// December 3,1993
//
///////////////////////////////////////////////////////////////////////////////
#ifndef CONTROLUNIT_HXX
#define CONTROLUNIT_HXX
#include "String.h"
#include "DataPath.hxx"
///////////////////////////////////////////////////////////////////////////////
// The Control Unit for the Hector 1600 CPU
///////////////////////////////////////////////////////////////////////////////
class ControlUnit {
private:
// Mnemonic to be added to trace record after opcode decoded and executed
String mnemonic;
// Routine to Execute instructions
const char* ControlUnit::ExecuteGroup1(int trace_flag);
const char* ControlUnit::ExecuteGroup2(int trace_flag);
const char* ControlUnit::ExecuteGroup3(int trace_flag);
const char* ControlUnit::ExecuteBRA(int trace_flag);
const char* ControlUnit::ExecuteJSR(int trace_flag);
const char* ControlUnit::ExecuteSWAP(int trace_flag);
const char* ControlUnit::ExecuteCLR(int trace_flag);
const char* ControlUnit::ExecuteMOVE(int trace_flag);
const char* ControlUnit::ExecuteTEST(int trace_flag);
const char* ControlUnit::ExecuteSTF(int trace_flag);
const char* ControlUnit::ExecuteLDF(int trace_flag);
const char* ControlUnit::ExecutePUSH(int trace_flag);
const char* ControlUnit::ExecuteSEC(int trace_flag);
const char* ControlUnit::ExecuteCLC(int trace_flag);
const char* ControlUnit::ExecuteSEI(int trace_flag);
const char* ControlUnit::ExecuteCLI(int trace_flag);
const char* ControlUnit::ExecuteRTI(int trace_flag);
const char* ControlUnit::ExecuteSWI(int trace_flag);
const char* ControlUnit::ExecuteEXCH(int trace_flag);
const char* ControlUnit::ExecuteSRCH(int trace_flag);
// Register transfer functions
const char* reg_to_reg(int reg_a, int reg_b);
const char* reg_indirect_to_reg(int reg_a, int reg_b);
const char* reg_to_reg_indirect(int reg_a, int reg_b);
const char* reg_to_mar_indirect(int reg);
const char* mar_indirect_to_reg(int reg);
const char* mdr_to_mar_indirect();
const char* inc_reg(int reg);
const char* reg_op_reg_to_reg(int reg_a, int reg_b);
const char* reg_op_reg_to_mdr(int reg_a, int reg_b);
const char* reg_plus_reg_to_reg(int reg_a, int reg_b);
const char* reg_plus_reg_to_mar(int reg_a, int reg_b);
const char* dec_reg(int reg);
const char* reg_op_reg(int reg_a, int reg_b);
const char* op_reg_to_reg(int reg);
const char* op_reg_to_mdr(int reg);
const char* swap_reg_to_reg(int reg_a, int reg_b);
const char* swap_reg_to_mdr(int reg);
const char* clr_reg(int reg);
const char* clr_mdr();
const char* flags_to_reg(int reg);
const char* flags_to_mdr();
const char* reg_to_flags(int reg);
const char* pass_reg_to_reg(int reg_a, int reg_b);
const char* reg_to_reg_indirect_with_inc(int reg_a, int reg_b);
const char* mdr_to_mar_indirect_with_inc(int reg);
const char* reg_to_reg_indirect_with_dec(int reg_a, int reg_b);
// Decode and execute the instruction in IR
const char* DecodeAndExecute(int trace_flag);
public:
// CPU's data path
DataPath& data_path;
// Class Constructor
ControlUnit(DataPath& d)
: data_path(d)
{}
~ControlUnit()
{}
// Fetch, decode, and execute the next instruction
const char* ExecuteInstruction(String& trace_record, int trace_flag);
};
#endif